1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication process therefor, and more particularly, to a semiconductor device having a monitor pattern for measuring a characteristic of a transistor for a memory cell included in the memory cell of a DRAM (Dynamic Random Access Memory) and to a fabrication process therefor.
2. Description of the Background Art
First of all, description will be given of a semiconductor device having a prior art monitor pattern.
FIG. 48 is a plan view showing a configuration of a semiconductor device having a prior art monitor pattern. FIGS. 49, 50, 51 and 52 are schematic sectional views taken on respective lines ILxe2x80x94IL, Lxe2x80x94L, LIxe2x80x94LI and LIIxe2x80x94LII of FIG. 48.
Referring mainly to FIG. 48, in a monitor area, similar to a memory cell area, there are arranged plural conductive layers 105 corresponding to word lines and plural conductive layers 111 and 111a corresponding to bit lines such that any one of the former and any one of the latter intersect orthogonally with each other. Monitor transistors MT are located in the vicinity of respective corresponding intersections of plural conductive layers 105 and plural conductive layers 111 and 111a. Each of monitor transistors MT has a configuration equivalent to a transistor constituting a memory cell (hereinafter referred to as a memory cell transistor).
Referring to FIGS. 48 to 52, a monitor transistor MT is formed on a surface of a silicon substrate 101 isolated electrically by a trench isolation 102. Monitor transistor MT is a MOS (Metal Oxide Semiconductor) transistor and include a pair of source/drain regions 103, a gate insulating layer 104 and a gate electrode layer 105.
A pair of source/drain regions 103 are formed spaced apart from each other on the surface of silicon substrate 101 and have an LDD (Lightly Doped Drain) structure. Gate electrode layer 105 is formed on a region sandwiched by source/drain regions 103 of the pair with gate insulating layer 104 interposing therebetween. Insulating layers 106 and 107 are formed so as to cover the top and side surfaces of gate electrode layer 105.
An interlayer insulating layer 108 is formed so as to cover plural monitor transistors MT and has holes 108a reaching to source/drain regions 103 formed therein. Holes 108a are each filled with a pad layer 109b or 109c. An interlayer insulating layer 110 is formed on interlayer insulating layer 108 and has a hole 110a reaching pad layer 109b formed therein.
A lead interconnection layer 111a is formed on interlayer insulating layer 110 so as to be electrically connected to pad layer 109b through hole 110a. Furthermore, plural conductive layers 111 are formed on interlayer insulating layer 110 in addition to lead interconnection layer 111a. An interlayer insulating layer 112 is formed so as to cover lead interconnection layer 111a and plural conductive layers 111. Interlayer insulating layer 112 and interlayer insulating layer 110 have a hole 112a reaching pad layer 109c therethrough, and a plug layer 113 is formed in holes 112a. 
An interlayer insulating layer 114 is formed on interlayer insulating layer 112 and has a hole 114a formed therein. A lead interconnection layer 115a is formed along an inner wall of hole 114a and electrically connected to pad layer 109c through plug layer 113. Note that a conductive layer 115 serving as many dummy storage nodes is formed in addition to lead interconnection layer 115a. There are formed an insulating layer 116 constituted of the same layer as is a capacitor dielectric layer and a conductive layer 117 constituted of the same layer as is a cell plate so as to cover an upper surface of lead interconnection layer 131, and an insulating layer 118 is formed on conductive layer 117.
In order to monitor a characteristic of monitor transistor MT, source/drain regions 103 of a pair are lead out by respective lead interconnection layers 111a and 115a. Lead interconnection layers 111a and 115a are electrically connected to bonding pad layers, which is the uppermost layer.
In order to monitor a characteristic of a prior art monitor transistor MT, a monitor signal is inputted from a bonding pad exposed on a wafer surface after all the wafer process is over. The monitor signal is given to a pair of source/drain regions 103 of monitor transistor MT from the bonding pad through lead interconnection layer 111a or 115a, and thereby, the characteristic of monitor transistor MT is monitored.
Along with progress in miniaturization of a semiconductor device, especially a DRAM, in structure in recent years, however, it has been requested to monitor a characteristic of a memory cell transistor with more of correctness. For example, parasitic resistance of lead sections of source/drain regions 103 of a monitor transistor MT and direct contact resistance parasitizing source/drain regions 103 should be considered so as to be the smallest possible value since such parasitic resistance works as obstacles in correct evaluation of a transistor characteristic.
Furthermore, in order to perform quick feedback in development of a semiconductor device, a transistor characteristic is desirably evaluated not only in the final stage of a wafer process but also at a stage, particularly as early as possible, into a wafer process from the start thereof.
The present invention has been made in order to respond to a request as described above, and it is accordingly, an object of the present invention to provide a semiconductor device capable of monitoring a transistor characteristic correctly and easily by reducing parasitic resistance, further, at an early stage in a wafer process; and a method of manufacturing therefor.
A semiconductor device of the present invention is a semiconductor device having a monitor pattern for measuring a characteristic of a memory cell transistor included in a memory cell, having a monitor transistor; a first lead interconnection layer; and a second lead interconnection layer. The monitor transistor has a source impurity region and a drain impurity region. The first lead interconnection layer is electrically connected to the source impurity region and has a section to which a needle of a prober can be connected externally. The second lead interconnection layer is electrically connected to the drain impurity region and has a section to which a needle of a prober can be connected externally. The first and second lead interconnection layers are formed on the same layer and further, formed on the same layer as is one of a bit line conductive layer and a storage node conductive layer, electrically connected to the memory cell transistor.
According to a semiconductor device of the present invention, since the first and second lead interconnection layers have each sections to each of which the needle of a prober can be connected and are formed on the same layer as are a bit line and a storage node, a transistor characteristic can be monitored at a stage where the bit line and the storage node of a memory cell have been formed. Accordingly, since monitoring of a transistor characteristic can be performed at an early stage in a wafer process, thereby enabling quick feedback in development of a semiconductor device.
Furthermore, since no necessity arises for leading out the source and drain regions of a monitor transistor to the bonding pads in the uppermost layer, dissimilar to the prior art example, it is possible to reduce parasitic resistance of lead sections thereof, which makes it possible to monitor a transistor characteristic correctly and easily.
In the above semiconductor device, a material of the first and second lead interconnection layers are preferably made from metal.
With adoption of metal as material of the interconnection layers, the parasitic resistance of the lead sections can be further reduced, thereby enabling more correct monitoring of a transistor characteristic.
In the semiconductor device, the first and second lead interconnection layers are formed on the same layer as is the storage node conductive layer.
With such a structure, a detailed analysis of a transistor can be performed by comparative evaluation with one pattern.
In the above semiconductor device, the first and second lead interconnection layers are electrically connected to the bit line conductive layer and the storage node conductive layer, respectively, through pad layers.
With such a structure, a large margin for photolithography can be ensured on connection of a lead interconnect to a lower layer.
In the above semiconductor device, it is preferable that the pad layers are connected to one of the source impurity region and drain impurity region of one of the monitor transistor and to one of the source impurity region and drain impurity region of another the monitor transistor, and one of the first and second lead interconnection layers is connected to the almost middle section of the top surface of a pad layer.
With such a structure, a larger margin for photolithography can be ensured on connection of a lead interconnect to a lower layer.
A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device having a monitor pattern for measuring a characteristic of a memory cell transistor included in a memory cell, including the following steps:
At first, a monitor transistor having a source impurity region and drain impurity region is formed. The first lead interconnection layer has a section which is electrically connected to the source impurity region and to which a needle of a prober can be connected externally. The second lead interconnection layer has a section which is electrically connected to the drain impurity region and to which a needle of a prober can be connected externally. The first and second lead interconnection layers are formed from the same layer as is one of the bit line conductive layer and the storage node conductive layer.
According to a method of manufacturing a semiconductor device of the present invention, since the first and second lead interconnection layers have respective sections to each of which the needle of a prober can be connected externally and are formed from the same layer as is a bit line or a storage node, a transistor characteristic can be monitored after the bit line and the storage node are formed. For this reason, a transistor characteristic can be evaluated at an early stage in a wafer process and in turn, quick feedback can be performed in development of a semiconductor device.
Furthermore, since no necessity arises for leading out a source impurity region and a drain impurity region up to bonding pads of the uppermost layer, parasitic resistance of lead sections can be reduced, thereby enabling correct measurement of a transistor characteristic with ease.
In the above method of manufacturing a semiconductor device, the process preferably further includes: a step of forming pad layers for electrically connecting the first and second lead interconnection layers to the source impurity region and drain impurity region, respectively, of a monitor transistor. The pad layers are formed so as to be connected to one of the source impurity region and drain impurity region of one of the monitor transistor and to one of the source impurity region and drain impurity region of another of the monitor transistor.
With such a structure, a large margin for photolithography can be ensured on connection of a lead interconnect to a lower layer.
In the above method of manufacturing a semiconductor device, the pad layers are preferably formed by transferring a pattern of a pad photomask using a photolithographic technique. The pad photomask has a first pattern each of whose features is located in a region corresponding to one of the source impurity region and drain impurity region of one of the monitor transistor, a second pattern each of whose features is located in a region corresponding to one of the source impurity region and drain impurity region of another of the monitor transistor and a third pattern for connecting features of the first and second patterns.
With such a photomask applied, there can be formed the pad layers connecting one of the source region and drain region of one of the monitor transistor to one of the source region and drain region of another of the monitor transistor with each other.
In the above method of manufacturing a semiconductor device, the third pattern has a feature width narrower than do the first and second patterns.
With such a third pattern adopted, a transfer pattern corresponding to the third pattern is harder to be connected to a transfer pattern of a pattern other than the first and second patterns when in a transfer operation of a mask pattern, thereby enabling a process margin for photolithography to increase.
In the above method of manufacturing a semiconductor device, the center of the third pattern is preferably shifted from an imaginary line connecting the centers of corresponding features of the first and second patterns therebetween.
With such a structure, since it becomes possible to place features of the third pattern spaced apart from features of a pattern other than the first and second patterns, a large process margin for photolithography can be ensured.
In the above method of manufacturing a semiconductor device, one of the first and second lead interconnection layers is formed so as to be connected to the pad layer through a contact hole. The contact hole is formed such that an almost middle portion of the top surface of the pad layer is exposed by transferring a pattern of a hole photomask with a photolithographic technique.
Since, in such a way, the contact hole is formed so as to expose the almost middle portion of the top surface of the pad layer, a large process margin for photolithography can be ensured.
In the method of manufacturing a semiconductor device, it is preferable that the hole photomask has a hole pattern one of whose features is located in a region corresponding to said contact hole and the center of the one feature of the hole pattern is shifted from the center of a feature of a pad pattern constituted of features of the first to third patterns only along one direction.
With such a structure, since each feature of the hole pattern can be placed spaced apart from features of a different pattern formed on the hole photomask, a large process margin for photolithography can be ensured.
In the above method of manufacturing a semiconductor device, the center of a feature of the hole pattern is shifted from the center of a corresponding feature of the pad pattern along not only one direction but also a direction perpendicular to the one direction.
With such a structure, since each of feature of a hole pattern can be located spaced apart from features of a different pattern formed on a hole photomask along not only one direction but also a direction perpendicular to the one direction, a larger process margin for photolithography can be ensured.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.